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19-2456; Rev 0; 11/07
Low-Jitter, Precision Clock Generator with Two Outputs
General Description
The MAX3622 is a low-jitter precision clock generator optimized for networking applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) clock multiplier to generate high-frequency clock outputs for Ethernet and other networking applications. Maxim's proprietary PLL design features ultra-low jitter (0.36psRMS) and excellent power-supply noise rejection, minimizing design risk for network equipment. The MAX3622 has one LVPECL output and one LVCMOS output. It is available in a 16-pin TSSOP package and operates over the 0C to +70C temperature range.
Features
Crystal Oscillator Interface: 25MHz Typical Output Frequencies: 125MHz and 156.25MHz Low Jitter 0.14psRMS (1.875MHz to 20MHz) 0.36psRMS (12kHz to 20MHz) Excellent Power-Supply Noise Rejection No External Loop Filter Capacitor Required
MAX3622
Applications
Ethernet Networking Equipment
PART MAX3622CUE+
Ordering Information
TEMP RANGE 0C to +70C PINPACKAGE 16 TSSOP PKG CODE U16-2
Typical Application Circuit and Pin Configuration appear at end of data sheet.
+Denotes a lead-free package.
Block Diagram
QAC_OE RESET LOGIC/POR RESET LVCMOS BUFFER
MAX3622
27pF X_IN 25MHz X_OUT 33pF CRYSTAL OSCILLATOR PFD
/5
QA_C
625MHz FILTER RESET VCO
RESET
RESET
QB_OE LVPECL BUFFER QB QB
/ 25
/4
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Jitter, Precision Clock Generator with Two Outputs MAX3622
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range VCC, VCCA, VDDO_A, VCCO_B ...............................................-0.3V to +4.0V Voltage Range at QAC_OE, QB_OE, RES1, RES2 ............................................-0.3V to (VCC + 0.3V) Voltage Range at X_IN Pin ....................................-0.3V to +1.2V Voltage Range at GNDO_A...................................-0.3V to +0.3V Voltage Range at X_OUT Pin ......................-0.3V to (VCC - 0.6V) Current into QA_C ............................................................50mA Current into QB, QB...........................................................-56mA Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 11.1mW/C above +70C) .......889mW Operating Junction Temperature Range ...........-55C to +150C Storage Temperature Range .............................-65C to +160C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER Power-Supply Current Input Capacitance Input Logic Bias Resistor SYMBOL ICC CIN RBIAS VCC 1.13 VCC 1.85 0.6 20% to 80% 200 48 VIH VIL I IH I IL VOH VOL VIN = VCC VIN = 0V QA_C sourcing 12mA QA_C sinking 12mA (Note 4) (Note 4) 250 42 500 50 14 -80 2.6 0.4 1000 58 2.0 0.8 80 (Note 3) CONDITIONS MIN TYP 70 2 50 VCC 0.98 VCC 1.7 0.72 350 50 VCC 0.83 VCC 1.55 0.9 600 52 MAX 90 UNITS mA pF k
CONTROL INPUT CHARACTERISTICS (QAC_OE, QB_OE PINS)
LVPECL OUTPUT SPECIFICATIONS (QB, QB PINS) Output High Voltage Output Low Voltage Peak-to-Peak Output-Voltage Swing (Single-Ended) Output Rise/Fall Time Output Duty-Cycle Distortion LVCMOS/LVTTL INPUT SPECIFICATIONS (QAC_OE, QB_OE PINS) Input-Voltage High Input-Voltage Low Input High Current Input Low Current Output High Voltage Output Low Voltage Output Rise/Fall Time Output Duty-Cycle Distortion Output Impedance V V A A V V ps % VOH VOL V V VP-P ps %
LVCMOS OUTPUT SPECIFICATIONS (QA_C PIN)
2
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Low-Jitter, Precision Clock Generator with Two Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER VCO Frequency Range Random Jitter Deterministic Jitter Induced by Power-Supply Noise (Notes 5, 6) Spurs Induced by Power-Supply Noise (Note 6) Nonharmonic and Subharmonic Spurs f = 1kHz Clock Output SSB Phase Noise at 125MHz f = 10kHz f = 100kHz f = 1MHz f > 10MHz RJRMS 12kHz to 20MHz 1.875MHz to 20MHz LVPECL output LVCMOS output LVPECL output LVCMOS output SYMBOL CONDITIONS MIN 620 TYP 625 0.36 0.14 4 psP-P 19 -57 -47 -70 -124 -126 -130 -145 -153 dBc/Hz dBc dBc MAX 648 1.0 UNITS MHz psRMS
MAX3622
CLOCK OUTPUT AC SPECIFICATIONS
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
A series resistor of up to 10.5 is allowed between VCC and VCCA for filtering supply noise when system power-supply tolerance is VCC = 3.3V 5%. See Figure 2. LVPECL terminated with 50 load connected to VTT = VCC - 2V. Both outputs enabled and unloaded. Measured using setup shown in Figure 1 with VCC = 3.3V 5%. Measured with Agilent DSO81304A 40GS/s real-time oscilloscope. Measured with 40mVP-P, 100kHz sinusoidal signal on the supply with VCCA connected as shown in Figure 2.
MAX3622
QA_C
36
499 4.7pF
0.1F Z0 = 50
OSCILLOSCOPE
50
Figure 1. LVCMOS Output Measurement Setup
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Low-Jitter, Precision Clock Generator with Two Outputs MAX3622
Typical Operating Characteristics
(Typical values are at VCC = +3.3V, TA = +25C, crystal frequency = 25MHz.)
DIFFERENTIAL OUTPUT WAVEFORM AT 156.25MHz (LVPECL OUTPUT)
MAX3622 toc02 MAX3622 toc01
SUPPLY CURRENT vs. TEMPERATURE
150 125 SUPPLY CURRENT (mA) BOTH OUTPUTS ACTIVE AND TERMINATED 100 75 BOTH OUTPUTS ACTIVE AND UNTERMINATED 50 25 0 0 10 20 30 40 50 60 70
OUTPUT WAVEFORM AT 125MHz (LVCMOS OUTPUT)
MAX3622 toc03
MEASURED USING 50 OSCILLOSCOPE INPUT THROUGH NETWORK SHOWN IN FIGURE 1 AMPLITUDE (200mv/div) AMPLITUDE (50mV/div)
1ns/div
1ns/div
AMBIENT TEMPERATURE (C)
QB PHASE NOISE (156.25MHz CLOCK FREQUENCY)
MAX3622 toc04
QA_C PHASE NOISE (125MHz CLOCK FREQUENCY)
-90 -100 -110 -120 -130 -140 -150 -160
MAX3622 toc05
-80 NOISE POWER DENSITY (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 0.1 1 10 100
-80 NOISE POWER DENSITY (dBc/Hz)
1000 10,000 100,000
0.1
1
10
100
1000 10,000 100,000
OFFSET FREQUENCY (kHz)
OFFSET FREQUENCY (kHz)
4
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Low-Jitter, Precision Clock Generator with Two Outputs
Pin Description
PIN 1 2 3 4 5, 6 7 8 9, 15 10 11 12 13 14 16 NAME QAC_OE GNDO_A QA_C VDDO_A FUNCTION LVCMOS/LVTTL Input. Enables/disables QA_C clock output. Connect pin high to enable QA_C. Connect low to set QA_C to a high-impedance state. Has internal 50k input impedance. Ground for QA_C Output. Connect to supply ground. LVCMOS Clock Output Power Supply for QA_C Clock Output. Connect to +3.3V. Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering, this pin can connect to VCC through 10.5 as shown in Figure 2 (requires VCC = +3.3V 5%). Core Power Supply. Connect to +3.3V. Supply Ground Crystal Oscillator Output Crystal Oscillator Input Power Supply for QB Clock Output. Connect to +3.3V. LVPECL, Inverting Clock Output LVPECL, Noninverting Clock Output LVCMOS/LVTTL Input. Enables/disables QB clock output. Connect pin high to enable LVPECL clock output QB. Connect low to set QB to a logic 0. Has internal 50k input impedance.
MAX3622
RES1, RES2 Reserved. Do not connect. VCCA VCC GND X_OUT X_IN VCCO_B QB QB QB_OE
Detailed Description
The MAX3622 is a low-jitter clock generator designed to operate at Ethernet frequencies. It consists of an onchip crystal oscillator, PLL, LVCMOS output buffer, and an LVPECL output buffer. Using a 25MHz crystal as a reference, the internal PLL generates a high-frequency output clock with excellent jitter performance.
to the reference clock. The high-frequency VCO output clock is sent to the output dividers. To minimize noiseinduced jitter, the VCO supply (VCCA) is isolated from the core logic and output buffer supplies.
Output Dividers
The output dividers are set to divide-by-five for the LVCMOS output QA_C and divide-by-four for the LVPECL output QB.
Crystal Oscillator
An integrated oscillator provides the low-frequency reference clock for the PLL. This oscillator requires a 25MHz crystal connected between X_IN and X_OUT.
LVPECL Driver
The differential PECL buffer (QB) is designed to drive transmission lines terminated with 50 to VCC - 2.0V. The output goes to a logic 0 when disabled.
PLL
The PLL takes the signal from the crystal oscillator and synthesizes a low-jitter, high-frequency clock. The PLL contains a phase-frequency detector (PFD), a lowpass filter, and a voltage-controlled oscillator (VCO). The VCO output is connected to the PFD input through a feedback divider. The PFD compares the reference frequency to the divided-down VCO output (fVCO/25) and generates a control signal that keeps the VCO locked
LVCMOS Driver
QA_C, the LVCMOS output, is designed to drive a single-ended high-impedance load. This output goes to a high-impedance state when disabled.
Reset Logic/POR
During power-on, the power-on reset (POR) signal is generated to synchronize all dividers.
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Low-Jitter, Precision Clock Generator with Two Outputs MAX3622
Applications Information
+3.3V 5% VCC 0.01F 10.5 VCCA 0.01F 10F
Power-Supply Filtering
The MAX3622 is a mixed analog/digital IC. The PLL contains analog circuitry susceptible to random noise. In addition to excellent on-chip power-supply noise rejection, the MAX3622 provides a separate powersupply pin, VCCA, for the VCO circuitry. Figure 2 illustrates the recommended power-supply filter network for V CCA . The purpose of this design technique is to ensure clean input power supply to the VCO circuitry and to improve the overall immunity to power-supply noise. This network requires that the power supply is +3.3V 5%. Decoupling capacitors should be used on all other supply pins for best performance.
Figure 2. Analog Supply Filtering
Crystal Selection
The crystal oscillator is designed to drive a fundamental mode, AT-cut crystal resonator. See Table 1 for recommended crystal specifications. See Figure 4 for external capacitor connection.
C9
Y1 25MHz CRYSTAL
Crystal Input Layout and Frequency Stability
The crystal, trace, and two external capacitors should be placed on the board as close as possible to the MAX3622's X_IN and X_OUT pins to reduce crosstalk of active signals into the oscillator. The layout shown in Figure 3 gives approximately 3pF of trace plus footprint capacitance per side of the crystal (Y1). The dielectric material is FR-4 and dielectric thickness of the reference board is 15 mils. Using a 25MHz crystal and the capacitor values of C10 = 27pF and C9 = 33pF, the measured output frequency accuracy is -10ppm at +25C ambient temperature.
MAX3622
C 10
Figure 3. Crystal Layout
Table 1. Crystal Selection Parameters
PARAMETER Crystal Oscillation Frequency Shunt Capacitance Load Capacitance Equivalent Series Resistance (ESR) Maximum Crystal Drive Level SYMBOL f OSC CO CL RS MIN TYP 25 2.0 18 50 300 W 7.0 MAX UNITS MHz pF pF
6
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Low-Jitter, Precision Clock Generator with Two Outputs
Interfacing with LVPECL Outputs
27pF X_IN 25MHz CRYSTAL (CL = 18pF) X_OUT 33pF
MAX3622
The equivalent LVPECL output circuit is given in Figure 7. This output is designed to drive a pair of 50 transmission lines terminated with 50 to VTT = VCC - 2V. If a separate termination voltage (VTT) is not available, other termination methods can be used such as shown in Figures 5 and 6. Unused outputs should be disabled and may be left open. For more information on LVPECL terminations and how to interface with other logic families, refer to Maxim Application Note HFAN-01.0: Introduction to LVDS, PECL, and CML.
Figure 4. Crystal, Capacitors Connection
Interface Models
Figure 7 and Figure 8 show examples of interface models.
VCC
+3.3V
130
130 HIGH IMPEDANCE QB 82 QB
MAX3622 QB
QB
Z0 = 50 Z0 = 50 82
Figure 5. Thevenin Equivalent of Standard PECL Termination
ESD STRUCTURES Z0 = 50 100 0.1F QB 150 150 DISABLE Z0 = 50 HIGH IMPEDANCE
0.1F QB
Figure 7. Simplified LVPECL Output Circuit Schematic
VDDO_A
MAX3622
NOTE: AC-COUPLING IS OPTIONAL.
10 IN 10 QA_C
Figure 6. AC-Coupled PECL Termination
ESD STRUCTURES GNDO_A
Figure 8. Simplified LVCMOS Output Circuit Schematic
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Low-Jitter, Precision Clock Generator with Two Outputs MAX3622
Layout Considerations
The inputs and outputs are critical paths for the MAX3622, and care should be taken to minimize discontinuities on these transmission lines. Here are some suggestions for maximizing the MAX3622's performance: * An uninterrupted ground plane should be positioned beneath the clock I/Os. * Supply and ground pin vias should be placed close to the IC and the input/output interfaces to allow a return current path to the MAX3622 and the receive devices. * Supply decoupling capacitors should be placed close to the MAX3622 supply pins. * Maintain 100 differential (or 50 single-ended) transmission line impedance out of the MAX3622. * Use good high-frequency layout techniques and a multilayer board with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to the MAX3622 Evaluation Kit for more information.
Typical Application Circuit
VCC +3.3V 5% 10.5 0.1F 0.1F 0.01F 0.1F
10F
VCC VCCA 0.01F
VCCO_B
VDDO_A QA_C 125MHz
36 Z0 = 50 ASIC
VCC
MAX3622
QAC_OE QB_OE X_OUT X_IN GND QB QB GNDO_A Z0 = 50 Z0 = 50 156.25MHz 50 50 (VCC - 2V) ASIC
25MHz (CL = 18pF) 33pF 27pF
8
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Low-Jitter, Precision Clock Generator with Two Outputs
Pin Configuration
TOP VIEW
QAC_OE GNDO_A QA_C VDDO_A RES1 RES2 VCCA VCC 1 2 3 4 5 6 7 8 + 16 15 14 13 QB_OE GND QB QB VCCO_B X_IN X_OUT GND
Chip Information
TRANSISTOR COUNT: 10,490 PROCESS: BiCMOS
MAX3622
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE 16 TSSOP DOCUMENT NO. 21-0066
MAX3622
12 11 10 9
TSSOP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
(c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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